1. Field of Invention
The present invention pertains to the field of non-volatile memories. More particularly, this invention relates to a non-volatile memory array that includes self-aligned dual function bit lines and asymmetrical source and drain junctions.
2. Description of the Related Art
Prior non-volatile memories typically include an array of memory cells which are accessible via a matrix of control lines. Such control lines typically include dedicated bit lines that couple to the drain regions of the memory cells. In addition, such control lines usually include word lines that couple to the control gates of the memory cells and dedicated Vss lines that couple to the source regions of the memory cells.
Such dedicated bit lines are typically formed from a metal such as aluminum. Such word lines are commonly formed of a polysilicon material or polycide material that includes a refractory metal. Such prior memory arrays typically include drain contact areas that provide electrical coupling between the drain regions of the memory cells and the dedicated bit lines.
Such drain contact areas are usually defined by the photo lithographic printing equipment employed in the particular memory device manufacturing process. Typically, such printing equipment is characterized by a minimum feature size for forming areas on the memory array including the drain contact areas. As a consequence, each drain contact area consumes a fixed minimum area of integrated circuit die space according to the minimum feature size inherent with the particular printing equipment.
Unfortunately, the integrated circuit die space consumed by such drain contact features limits the density of a memory array for a given area of integrated circuit die space. Such density limitations commonly require that high capacity memory arrays be implemented on larger silicon substrates. Such larger silicon substrates usually increases the overall cost of such memory devices.
One prior method for eliminating such drain contact features in a nonvolatile memory array is to employ an array architecture that may be referred to as a virtual ground architecture. Such a virtual ground array includes dual-function control lines that function as both bit lines and Vss lines. Such a virtual ground array usually obviates the need for forming drain contact features for dedicated bit lines.
The dual function control lines in prior virtual ground memory arrays are typically formed by masking, dopant implant, and thermal diffusion process steps. Such a process that employs masking and thermal diffusion process steps usually causes migration of the implanted dopant into areas outside of the control line areas defined by the mask. Such dopant migration typically requires increased spacing of control lines in order to provide electrical isolation of the control lines from other areas of the memory array. Unfortunately, such increased spacing of control lines usually reduces the density of memory cells formed by such a process.
The present invention, roughly described, provides for a flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by a plurality of field oxide islands. A first junction and a second junction are then formed in each of a set of source/drain regions located between the stacked gate strips and between the field oxide islands. A chemical etch is then applied to form the field oxide islands into pairs of oxide spacers and to expose a continuous strip of the silicon substrate between the oxide spacers and over the source/drain regions. A dopant is implanted into the continuous strip to form a control line to the first and second junctions such that the control line is aligned by the oxide spacers.
One embodiment of the flash memory device includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, a first junction in each of the source/drain regions, a second junction in each of the source/drain regions and a dual function control line in the source/drain regions. The first junction and second junction are asymmetrical. Another embodiment of the flash memory device includes a stacked gate structure, a first source/drain region, a first junction in the first source/drain region, a second junction in the first source/drain region, a first dual function control line in the first source/drain region, a second source/drain region, a third junction in the second source/drain region, a fourth junction in the second source/drain region and a second dual function control line in the second source/drain region.
A flash memory of the present invention can be operated by one of many various alternative methods. One embodiment method includes programming a flash memory cell using a first source/drain region as a drain and a second source/drain region as a source; and reading the flash memory cell using the first source/drain region as the source and the second source/drain region as the drain. In another embodiment, the method includes connecting the second dual function control to a ground potential while programming the flash memory, and connecting the first dual function control line to the ground potential while reading the flash memory cell.
In yet another embodiment, the method of operating the flash memory cell includes programming the flash memory cell using the first source/drain region as a drain and the second source/drain region as a source such that the step of programming includes transferring electrons from the floating gate to the drain.
The flash memory is read using the second source/drain region as a drain and the first source/drain region as a source.
Other objects, features and advantages of the present invention will be apparent from the detailed description that follows.